View LTM9001-AX10_2364259.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltm9001-ax/ltm9001-bx 1 9001fc typical application features applications description 16-bit if/baseband receiver subsystem the ltm ? 9001 is an integrated system in a package (sip) that includes a high-speed 16-bit a/d converter, matching network, anti-aliasing ? lter and a low noise, differential ampli? er with ? xed gain. it is designed for digitizing wide dynamic range signals with an intermediate frequency (if) range up to 300mhz. the ampli? er allows either ac- or dc-coupled input drive. a lowpass or bandpass ? lter network can be implemented with various bandwidths. contact linear technology regarding semi-custom con? gurations. the ltm9001 is perfect for if receivers in demanding communications applications, with ac performance that includes 72dbfs noise ? oor and 82db spurious free dynamic range (sfdr) at 162.5mhz (ltm9001-aa). the digital outputs can be either differential lvds or single- ended cmos. there are two format options for the cmos outputs: a single bus running at the full data rate or two demultiplexed buses running at half data rate. a separate output power supply allows the cmos output swing to range from 0.5v to 3.3v. the differential enc + and enc C inputs may be driven with a sine wave, pecl, lvds, ttl or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. simpli? ed if receiver channel n integrated 16-bit, high-speed adc, passive filter and fixed gain differential ampli? er n up to 300mhz if range lowpass and bandpass filter versions n low noise, low distortion ampli? ers fixed gain: 8db, 14db, 20db or 26db 50 , 200 or 400 input impedance n 75db snr, 83db sfdr (ltm9001-ad) n integrated bypass capacitance, no external components required n optional internal dither n optional data output randomizer n lvds or cmos outputs n 3.3v single supply n power dissipation: 1.65w n clock duty cycle stabilizer n 11.25mm 11.25mm 2.32mm lga package n telecommunications n high sensitivity receivers n cellular base stations n spectrum analyzers 64k point fft, f in = 162.4mhz, C1dbfs, pga = 1 9001 ta01 clkout of lo v cc v dd = 3.3v enc + enc C adc control pins differential fixed gain amplifier 16-bit 130msps adc rf in C in + ltm9001 sense gnd d15 ? ? ? d0 0v dd = 0.5v to 3.6v ognd cmos or lv d s saw anti-alias filter amplitude (dbfs) C80 C60 C40 C20 0 9001 ta01b C100 C120 hd2 hd3 frequency (mhz) 010 30 40 20 50 60 ltm9001-aa l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners.
ltm9001-ax/ltm9001-bx 2 9001fc pin configuration absolute maximum ratings supply voltage (v cc ) ................................ ?0.3v to 3.6v supply voltage (v dd ) ................................... ?0.3v to 4v digital output supply voltage (ov dd ) .......... ?0.3v to 4v analog input current (in + , in ? ) ............................10ma digital input voltage (except ampshdn) ................. ?0.3v to (v dd + 0.3v) digital input voltage (ampshdn) ..............................?0.3v to (v cc + 0.3v) digital output voltage ................?0.3v to (ov dd + 0.3v) operating temperature range ltm9001c................................................ 0c to 70c ltm9001i .............................................?40c to 85c storage temperature range ...................?45c to 125c maximum junction temperature........................... 125c (notes 1, 2) order information lead free finish part marking* package description temperature range ltm9001cv-aa#pbf ltm9001v-aa 81-lead (11.25mm 11.25mm 2.3mm) lga 0c to 70c ltm9001iv-aa#pbf ltm9001v-aa 81-lead (11.25mm 11.25mm 2.3mm) lga ?40c to 85c ltm9001cv-ad#pbf ltm9001v-ad 81-lead (11.25mm 11.25mm 2.3mm) lga 0c to 70c ltm9001iv-ad#pbf ltm9001v-ad 81-lead (11.25mm 11.25mm 2.3mm) lga ?40c to 85c ltm9001cv-ba#pbf ltm9001v-ba 81-lead (11.25mm 11.25mm 2.3mm) lga 0c to 70c ltm9001iv-ba#pbf ltm9001v-ba 81-lead (11.25mm 11.25mm 2.3mm) lga ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ electrical characteristics symbol parameter conditions min typ max units g diff gain dc, ltm9001-aa f in = 162.5mhz (note 3) l 19.1 19.7 19 20.3 db db dc, ltm9001-ad f in = 70mhz (note 3) l 13.4 14 13.5 14.7 db db dc, ltm9001-ba f in = 140mhz (note 3) l 7.1 8.2 7.8 9.4 db db g temp gain temperature drift v in = maximum, (note 3) 2 mdb/c the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) in ? 1 j h g f e d c b a 234 lga package t jmax = 125c, q ja = 15c/w, q jctop = 19c/w q ja derived from 60mm s 70mm pcb with 4 layers weight = 0.71g 56789 data top view all else = gnd control ognd ov dd v cc dnc v dd ognd control ov dd ognd enc + in + enc ?
ltm9001-ax/ltm9001-bx 3 9001fc symbol parameter conditions min typ max units v incm input common mode voltage range (in + + in C )/2 1.0C1.6 v v in input voltage range at C1dbfs ltm9001-aa at 162.5mhz ltm9001-ad at 70mhz ltm9001-ba at 140mhz 233 424 820 mv p-p mv p-p mv p-p r indiff differential input impedance ltm9001-aa ltm9001-ad ltm9001-ba 200 200 400 c indiff differential input capacitance includes parasitic 1 pf v os offset error (note 6) including ampli? er and adc (ltm9001-aa) including ampli? er and adc (ltm9001-ad) including ampli? er and adc (ltm9001-ba) l l l C8 C11 C20 C3.2 C6 C10 C0.5 C0.5 C0.5 mv mv mv offset drift including ampli? er and adc 10 v/c full-scale drift internal reference external reference 30 15 ppm/c ppm/c cmrr common mode rejection ratio 60 db i sense sense input leakage current 0v < sense < v dd l C3 3 a i mode mode pin pull-down current to gnd 10 a i lv d s lvds pin pull-down current to gnd 10 a t ap sample-and-hold acquisition delay time 1 ns t jitter sample-and-hold acquisition delay time jitter 70 fs rms electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) parameter conditions min typ max units resolution (no missing codes) l 16 bits integral linearity error differential input ltm9001-ax (notes 5, 7) differential input ltm9001-ba (notes 5, 7) l l 2.4 8 10 lsb lsb differential linearity error differential input (notes 5, 7) l 0.3 1 lsb transition noise external reference 1 lsb rms converter characteristics the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units snr signal-to-noise ratio 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa l 67.2 72 68.5 dbfs dbfs 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad l 71.2 75 72 dbfs dbfs 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba l 67 69.2 67.2 dbfs dbfs dynamic accuracy the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4)
ltm9001-ax/ltm9001-bx 4 9001fc symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage l 0.2 v v icm common mode input voltage internally set externally set 1.2 1.6 3.1 v v r in input resistance 100 c in input capacitance (note 7) 3 pf digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) dynamic accuracy the l indicates speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. a in = C1dbfs. (note 4) symbol parameter conditions min typ max units sfdr spurious free dynamic range, 2nd or 3rd harmonic 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa l 72 78 82 dbc dbc 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad l 72.6 83 86 dbc dbc 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba l 64 72 82 dbc dbc sfdr spurious free dynamic range 4th or higher 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa l 86 95 95 dbc dbc 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad l 84.5 95 98 dbc dbc 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba l 86 95 104 dbc dbc s/(n+d) signal-to-noise plus distortion ratio 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa l 67 71.4 68 dbfs dbfs 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad l 71.2 74.3 72 dbfs dbfs 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba l 64 67.5 66.4 dbfs dbfs sfdr spurious free dynamic range at C25dbfs, dither off 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa 90 93 dbfs dbfs spurious free dynamic range at C15dbfs, dither off 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad 85 87 dbfs dbfs spurious free dynamic range at C15dbfs, dither off 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba 91 92 dbfs dbfs sfdr spurious free dynamic range at C25dbfs, dither on 162.5mhz input (pga = 0) ltm9001-aa 162.5mhz input (pga = 1) ltm9001-aa l 90 95 100 dbfs dbfs spurious free dynamic range at C15dbfs, dither on 70mhz input (pga = 0) ltm9001-ad 70mhz input (pga = 1) ltm9001-ad l 90 92 88 dbfs dbfs spurious free dynamic range at C15dbfs, dither on 140mhz input (pga = 0) ltm9001-ba 140mhz input (pga = 1) ltm9001-ba l 90 95 96 dbfs dbfs imd 3 third order intermodulation distortion; 1mhz tone spacing, 2 tones at C7dbfs f in = 162.5mhz ltm9001-aa f in = 70mhz ltm9001-ad f in = 140mhz ltm9001-ba C78 C84 C84 db db db iip 3 equivalent third order input intercept point, 2 tone f in = 162.5mhz ltm9001-aa f in = 70mhz ltm9001-ad f in = 140mhz ltm9001-ba 24 26.5 29.2 dbm dbm dbm
ltm9001-ax/ltm9001-bx 5 9001fc the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units v dd adc analog supply voltage (note 8) l 3.135 3.3 3.465 v v cc ampli? er supply voltage 2.85 3.5 v i cc ampli? er supply current l 100 136 ma p shdn total shutdown power ampshdn = adcshdn = 3.3v 10 mw digital inputs and outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) symbol parameter conditions min typ max units logic inputs (dith, pga, adcshdn, rand) v ih high level input voltage v dd = 3.3v l 2v v il low level input voltage v dd = 3.3v l 0.8 v i in input current v in = 0v to v dd l 10 a c in input capacitance (note 7) 1.5 pf logic inputs (ampshdn) v ih high level input voltage v cc = 3.3v l 2v v il low level input voltage v cc = 3.3v l 0.8 v i ih input high current v in = 2v 1.3 a i il input low current v in = 0.8v 0.1 a c in input capacitance (note 7) 1.5 pf logic outputs (cmos mode) ov dd = 3.3v v oh high level output voltage v dd = 3.3v, i o = C10a v dd = 3.3v, i o = C200a l 3.1 3.299 3.29 v v v ol low level output voltage v dd = 3.3v, i o = 10a v dd = 3.3v, i o = 1.6ma l 0.01 0.1 0.4 v v i source output source current v out = 0v C50 ma i sink output sink current v out = 3.3v 50 ma ov dd = 2.5v v oh high level output voltage v dd = 3.3v, i o = C200a 2.49 v v ol low level output voltage v dd = 3.3v, i o = 1.6ma 0.1 v ov dd = 1.8v v oh high level output voltage v dd = 3.3v, i o = C200a 1.79 v v ol low level output voltage v dd = 3.3v, i o = 1.6a 0.1 v logic outputs (lvds mode) standard lvds v od differential output voltage 100 differential load l 247 350 454 mv v os output common mode voltage 100 differential load l 1.125 1.2 1.375 v low power lvds v od differential output voltage 100 differential load l 125 175 250 mv v os output common mode voltage 100 differential load l 1.125 1.2 1.375 v
ltm9001-ax/ltm9001-bx 6 9001fc symbol parameter conditions min typ max units f s sampling frequency (note 8) ltm9001-ax ltm9001-ba l l 1 1 130 160 mhz mhz t l enc low time (note 7) duty cycle stabilizer off (ltm9001-ax) duty cycle stabilizer off (ltm9001-ba) duty cycle stabilizer on (ltm9001-ax) duty cycle stabilizer on (ltm9001-ba) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns t h enc high time (note 7) duty cycle stabilizer off (ltm9001-ax) duty cycle stabilizer off (ltm9001-ba) duty cycle stabilizer on (ltm9001-ax) duty cycle stabilizer on (ltm9001-ba) l l l l 3.65 2.97 2.6 2.1 3.846 3.125 3.846 3.125 1000 1000 1000 1000 ns ns ns ns lvds output mode (standard and low power) t d enc to data delay (note 7) l 1.3 2.5 4 ns t c enc to clkout delay (note 7) l 1.3 2.5 4 ns t skew data to clkout skew (t c C t d ) (note 7) l C0.6 0 0.6 ns t rise output rise time 0.5 ns t fall output fall time 0.5 ns data latency 7 cycles the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4) power requirements symbol parameter conditions min typ max units standard lvds output mode ov dd output supply voltage (note 8) l 3 3.3 3.6 v i vdd analog supply current ltm9001-ax ltm9001-ba l l 400 465 500 550 ma ma i ovdd output supply current l 74 90 ma p diss power dissipation ltm9001-ax ltm9001-ba l l 1564 1779 1947 2112 mw mw low power lvds output mode ov dd output supply voltage (note 8) l 3 3.3 3.6 v i vdd analog supply current ltm9001-ax ltm9001-ba l l 400 465 500 550 ma ma i ovdd output supply current l 41 50 ma p diss power dissipation ltm9001-ax ltm9001-ba l l 1455 1670 1815 1980 mw mw cmos output mode ov dd output supply voltage (note 8) l 0.5 3.6 v i vdd analog supply current ltm9001-ax ltm9001-ba l l 380 460 450 530 ma ma p diss adc power dissipation ltm9001-ax ltm9001-ba l l 1320 1584 1650 1914 mw mw p diss(total) total power dissipation ltm9001-ax ltm9001-ba 1650 1914 mw mw
ltm9001-ax/ltm9001-bx 7 9001fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: gain is measured from in + /in C through the adc. the ampli? er gain is attenuated by the ? lter, (see the typical performance characteristics section for if frequency response). note 4: v cc = v dd = 3.3v, f sample = maximum sample frequency, lvds outputs, differential enc + /enc C = 2v p-p with 1.6v common mode, input range = C1dbfs with pga = 0 with differential drive, ac-coupled inputs, unless otherwise noted. note 5: integral nonlinearity is de? ned as the deviation of a code from a best ? t straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 6: offset error is the voltage applied between the in + and in C pins required to make the output code ? icker between 0000 0000 0000 0000 and 1111 1111 1111 1111. note 7: guaranteed by design, not subject to test. note 8: recommended operating conditions. timing characteristics symbol parameter conditions min typ max units cmos output mode t d enc to data delay (note 7) l 1.3 2.7 4 ns t c enc to clkout delay (note 7) l 1.3 2.7 4 ns t skew data to clkout skew (t c C t d ) (note 7) l C0.6 0 0.6 ns data latency full rate cmos demuxed 7 7 cycles cycles the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 4)
ltm9001-ax/ltm9001-bx 8 9001fc full-rate cmos output mode timing all outputs are single-ended and have cmos levels t ap analog input t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 enc C enc + clkouta clkoutb da0-da15, ofa db0-db15, ofb 9001 td02 high impedance n + 1 n + 2 n + 4 n + 3 n t h t d t c t l n C 7 n C 6 n C 5 n C 4 n C 3 analog input enc C enc + clkout C clkout + d0-d15, of 9001 td01 t ap n + 1 n + 2 n + 4 n + 3 n lvds output mode timing all outputs are differential and have lvds levels timing diagram
ltm9001-ax/ltm9001-bx 9 9001fc timing diagram demultiplexed cmos output mode timing all outputs are single-ended and have cmos levels t h t d t d t c t l n C 8 n C 6 n C 4 n C 7 n C 5 n C 3 enc C enc + clkouta clkoutb da0-da15, ofa db0-db15, ofb 9001 td03 t ap analog input n + 1 n + 2 n + 4 n + 3 n
ltm9001-ax/ltm9001-bx 10 9001fc typical performance characteristics best fit integral non-linearity (inl) vs output code differential non-linearity (dnl) vs output code 64k point fft, f in = 162.4mhz, C1dbfs, pga = 0, rand off, dither off 64k point fft, f in = 162.4mhz, C1dbfs, pga = 1, rand off, dither off 64k point 2-tone fft, f in = 161.5mhz, and 163.5mhz, C7dbfs, pga = 0, rand off, dither off if frequency response input impedance vs frequency shorted inputs histogram with 130k samples frequency (mhz) 120 filter gain (db) C4 C2 0 150 170 200 9001 g05 C6 C8 C10 130 140 160 180 190 frequency (mhz) 50 impedance magnitude () impedance phase (deg) 150 100 200 250 0 C45 C90 100 10 1000 9001 g04 magnitude phase adc output code 33484 count 5000 4000 3000 8000 7000 6000 9000 9001 g03 2000 1000 0 33504 33524 33544 adc output code 0 inl error (lsb) 1 0 3 4 2 5 49152 9001 g02 C1 C2 C3 C4 C5 16384 32768 65536 adc output code 0 dnl error (lsb) 0.1 0 0.3 0.4 0.2 0.5 49152 9001 g01 C0.1 C0.2 C0.3 C0.4 C0.5 16384 32768 65536 amplitude (dbfs) C80 C60 C40 C20 0 9001 g06 C100 C120 hd3 hd2 frequency (mhz) 010 30 40 20 50 60 amplitude (dbfs) C80 C60 C40 C20 0 9001 g07 C100 C120 hd2 hd3 frequency (mhz) 010 30 40 20 50 60 amplitude (dbfs) C80 C60 C40 C20 0 9001 g08 C100 C120 frequency (mhz) 010 30 40 20 50 60 (ltm9001-aa)
ltm9001-ax/ltm9001-bx 11 9001fc 64k point 2-tone fft, f in = 161.5mhz, and 163.5mhz, C15dbfs, pga = 0, rand off, dither off typical performance characteristics 64k point fft, f in = 162.4mhz, C15dbfs, pga = 0, rand off, dither off 64k point fft, f in = 162.4mhz, C15dbfs, pga = 0, rand off, dither on sfdr vs input level, f in = 162.4mhz, pga = 0, rand off, dither = off sfdr vs input level, f in = 162.4mhz, pga = 0, rand off, dither = on sfdr and snr vs sample rate, f in = 162.4mhz, C1dbfs, pga = 0, rand off, dither off sfdr vs input common mode voltage, f in = 162.4mhz, C1dbfs, pga = 0 sfdr vs v cc supply voltage, f in = 162.4mhz, C1dbfs, pga = 0 amplitude (dbfs) C80 C60 C40 C20 0 9001 g09 C100 C120 frequency (mhz) 010 30 40 20 50 60 amplitude (dbfs) C80 C60 C40 C20 0 9001 g10 C100 C120 frequency (mhz) 010 30 40 20 50 60 amplitude (dbfs) C80 C60 C40 C20 0 9001 g11 C100 C120 frequency (mhz) 010 30 40 20 50 60 input level (dbfs) C90 sfdr (dbc and dbfs) 60 80 100 120 140 C60 C40 9001 g12 40 20 0 C80 C70 C50 C30 C20 C10 0 sfdr dbc sfdr dbfs input common mode voltage (v) 0.5 sfdr (dbc) 75 80 85 90 2.0 3.0 9001 g15 70 65 60 1.0 1.5 2.5 v cc supply voltage (v) 2.8 sfdr (dbc) 78.0 78.5 79.0 79.5 80.0 80.5 81.0 3.1 3.5 9001 g16 77.5 77.0 76.5 76.0 75.5 2.9 3.0 3.2 3.3 3.4 input level (dbfs) C90 sfdr (dbc and dbfs) 60 80 100 120 140 C60 C40 9001 g13 40 20 0 C80 C70 C50 C30 C20 C10 0 sfdr dbc sfdr dbfs adc sample rate (msps) 0 sfdr (dbc) and snr (dbfs) 76 80 84 150 250 9001 g14 72 68 64 50 100 200 snr sfdr (ltm9001-aa)
ltm9001-ax/ltm9001-bx 12 9001fc typical performance characteristics (ltm9001-ad) input impedance vs frequency if frequency response 64k point fft, f in = 70mhz, C1dbfs, pga = 0, rand off, dither off 64k point 2-tone fft, f in = 70mhz, and ? n = 74mhz, C7dbfs per tone, pga = 0, rand off, dither off differential non-linearity (dnl) vs output code best fit integral non-linearity (inl) vs output code snr vs frequency output code 0 dnl error (lsb) C 0.2 0.0 0.2 0.4 0.6 0.8 1.0 49152 65536 9001 g25 C0.4 C0.6 C0.8 C1.0 16384 32768 output code 0 inl error (lsb) C2.0 C1.5 C1.0 C0.5 0.0 2.0 1.0 1.5 0.5 2.5 3.0 3.5 4.0 49152 65536 9001 g26 C2.5 C3.0 C3.5 C4.0 16384 32768 frequency (mhz) snr (db) 9001 g27 75 72 68 67 66 69 70 71 73 74 65 1 100 1000 10 frequency (mhz) impedance magnitude () 9001 g28 220 140 160 60 40 20 80 100 120 180 200 0 impedance phase (deg) 12 4 6 C4 C6 C8 C2 0 2 8 10 C10 1 100 1000 10 magnitude phase frequency (mhz) amplitude (dbfs) 9001 g29 0 C3 C7 C8 C9 C6 C5 C4 C2 C1 C10 40 50 80 90 100 60 70 frequency (mhz) amplitude (dbfs) 9001 g30 0 C30 C70 C80 C90 C100 C110 C60 C50 C40 C20 C10 C120 0 10 405060 20 30 hd2 hd3 frequency (mhz) amplitude (dbfs) 9001 g31 0 C30 C70 C80 C90 C100 C110 C60 C50 C40 C20 C10 C120 010 405060 20 30
ltm9001-ax/ltm9001-bx 13 9001fc typical performance characteristics (ltm9001-ba) input impedance vs frequency if frequency response 64k point fft, f in = 140mhz, C1dbfs, pga = 0, rand off, dither off 64k point fft, f in = 250mhz, C1dbfs, pga = 0, rand off, dither off 64k point 2-tone fft, f in = 136mhz, C7dbfs per tone, pga = 0, rand off, dither off differential non-linearity (dnl) vs output code best fit integral non-linearity (inl) vs output code snr vs frequency output code 0 dnl error (lsb) C 0.2 0.0 0.2 0.4 0.6 0.8 1.0 49152 65536 9001 g17 C0.4 C0.6 C0.8 C1.0 16384 32768 output code 0 inl error (lsb) C2.0 C1.5 C1.0 C0.5 0.0 2.0 1.0 1.5 0.5 2.5 3.0 3.5 4.0 49152 65536 9001 g18 C2.5 C3.0 C3.5 C4.0 16384 32768 frequency (mhz) snr (db) 9001 g19 71 65 57 55 53 59 61 63 67 69 51 1 100 1000 10 frequency (mhz) impedance magnitude () impedance phase (c) 9001 g20 400 250 50 100 150 200 300 350 0 0 C24 C16 C8 C32 1 100 1000 10 magnitude phase frequency (mhz) amplitude (dbfs) 9001 g21 0 C15 C25 C20 C10 C5 C30 1 100 1000 10 frequency (mhz) 0 amplitude (dbfs) C60 C50 C40 C30 C20 C10 0 50 60 9001 g22 C70 C80 C90 C100 C110 C120 10 20 30 40 hd2 hd3 frequency (mhz) 0 amplitude (dbfs) C60 C50 C40 C30 C20 C10 0 50 60 70 80 9001 g23 C70 C80 C90 C100 C110 C120 10 20 30 40 hd2 hd3 frequency (mhz) 0 amplitude (dbfs) C60 C50 C40 C30 C20 C10 0 50 60 9001 g24 C70 C80 C90 C100 C110 C120 10 20 30 40
ltm9001-ax/ltm9001-bx 14 9001fc supply pins v cc (pins e1, e2): 3.3v analog supply pin for ampli? er. the voltage on this pin provides power for the ampli? er stage only and is internally bypassed to gnd. v dd (pins e5, d5): 3.3v analog supply pin for adc. this supply is internally bypassed to gnd. ov dd (pins a6, g9): positive supply for the adc output drivers. this supply is internally bypassed to ognd. gnd (pins a1, a2, a4, b2, b4, c2, c4, d1, d2, d4, e4, f1, f2, f4, g2, g4, h2, h4, j1, j2, j4): analog ground. ognd (pins a5, a9, g8, j9): adc output driver ground. analog inputs in + (pin g1): positive (non-inverting) ampli? er input. in C (pin h1): negative (inverting) ampli? er input. dnc (pins c3, d3): do not connect. these pins are used for testing and should not be connected on the pcb. they may be soldered to unconnected pads and should be well isolated. the dnc pins connect to the signal path prior to the adc inputs; therefore, care should be taken to keep other signals away from these sensitive nodes. enc + (pin c1): positive differential encode input. the sampled analog input is held on the rising edge of enc + . this input is internally biased to 1.6v through a 6.2k resistor. output data can be latched on the rising edge of enc + . the encode pins have a differential 100 input impedance. enc C (pin b1): negative differential encode input. the sampled analog input is held on the falling edge of enc C . this input is internally biased to 1.6v through a 6.2k resistor. bypass to ground with a 0.1f capacitor for a single-ended encode signal. the encode pins have a differential 100 input impedance. control inputs sense (pin j3): reference mode select and external reference input. tie sense to v dd to select the internal 2.5v bandgap reference. an external reference of 2.5v or 1.25v may be used; both reference values will set the maximum full-scale input range. ampshdn (pin h3): power shutdown pin for ampli? er. this pin is a logic input referenced to analog ground. ampshdn = low results in normal operation. ampshdn = high results in powered down ampli? er with typically 3ma ampli? er supply current. mode (pin g3): output format and clock duty cycle stabilizer selection pin. connecting mode to 0v selects offset binary output format and disables the clock duty cycle stabilizer. connecting mode to 1/3v dd selects offset binary output format and enables the clock duty cycle stabilizer. connecting mode to 2/3v dd selects 2s complement output format and enables the clock duty cycle stabilizer. connecting mode to v dd selects 2s complement output format and disables the clock duty cycle stabilizer. rand (pin f3): digital output randomization selection pin. rand = low results in normal operation. rand = high selects d1 to d15 to be exclusive-ored with d0 (the lsb). the output can be decoded by again applying an xor operation between the lsb and all other bits. this mode of operation reduces the effects of digital output interference. pga (pin e3): programmable gain ampli? er control pin. pga = low selects the normal (maximum) input voltage range. pga = high selects a 3.5db reduced input range for slightly better distortion performance at the expense of snr. adcshdn (pin b3): power shutdown pin for adc. adcshdn = low results in normal operation. adcshdn = high results in powered down analog circuitry and the digital outputs are placed in a high impedance state. dith (pin a3): internal dither enable pin. dith = low disables internal dither. dith = high enables internal dither. refer to internal dither section of this data sheet for details on dither operation. lvds (pin f5): data output mode select pin. connecting lvds to 0v selects full rate cmos mode. connecting lvds to 1/3v dd selects demultiplexed cmos mode. connecting lvds to 2/3v dd selects low power lvds mode. connecting lvds to v dd selects standard lvds mode. pin functions
ltm9001-ax/ltm9001-bx 15 9001fc top view of lga pinout (looking through component) 9001 lga01 in C 1 j h g f e d c b a 23456789 data top view all else = gnd control ognd ov dd v cc dnc v dd ognd control ov dd ognd enc + in + enc C pin functions digital outputs for cmos mode, full rate or demultiplexed da0 to da15 (pins e9 to h5): digital outputs, a bus. da15 is the msb. output bus for full rate cmos mode and demultiplexed mode. clkouta (pin e8): inverted data valid output. clkouta will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the rising edge of clkouta. ofb (pin e6): over? ow/under? ow digital output for the b bus. ofb is high when an over? ow or under? ow has occurred on the b bus. ofb is in a high impedance state in full rate cmos mode. db0 to db15 (pins b5 to d9): digital outputs, b bus. db15 is the msb. active in demultiplexed mode. the b bus is in a high impedance state in full rate cmos mode. clkoutb (pin e7): data valid output. clkoutb will toggle at the sample rate in full rate cmos mode or at 1/2 the sample rate in demultiplexed mode. latch the data on the falling edge of clkoutb. ofa (pin g5): over? ow/under? ow digital output for the a bus. ofa is high when an over? ow or under? ow has occurred on the a bus. for lvds mode, standard or low power d0 C /d0 + to d15 C /d15 + (pins b5 to g6): lvds digital out- puts. all lvds outputs require differential 100 termination resistors at the lvds receiver. d15 + /d15 C is the msb. clkout C /clkout + (pins e6, e7): lvds data valid output. latch data on the rising edge of clkout + , falling edge of clkout C . of C /of + (pins h5, g5): over? ow/under? ow digital output. of is high when an over or under ? ow has occurred. pin con? guration (lvds outputs/cmos outputs) 123456 7 8 9 j gnd gnd sense gnd d14 + /da12 d14 C /da11 d12 + /da8 d12 C /da7 ognd hin C gnd ampshdn gnd of C /da15 d15 C /da13 d13 C /da9 d11 C /da5 d11 + /da6 gin + gnd mode gnd of + /ofa d15 + /da14 d13 + /da10 ognd ov dd f gnd gnd rand gnd lvds d9 C /da1 d9 + /da2 d10 C /da3 d10 + /da4 ev cc v cc pga gnd v dd clkout C /ofb clkout + /clkoutb d8 C /clkouta d8 + /da0 d gnd gnd dnc gnd v dd d6 C /db12 d6 + /db13 d7 C /db14 d7 + /db15 cenc + gnd dnc gnd d0 + /db1 d4 C /db8 d4 + /db9 d5 C /db10 d5 + /db11 benc C gnd adcshdn gnd d0 C /db0 d1 C /db2 d1 + /db3 d3 + /db7 d3 C /db6 a gnd gnd dith gnd ognd ov dd d2 C /db4 d2+/db5 ognd
ltm9001-ax/ltm9001-bx 16 9001fc functional block diagram 9001 bd clkout + clkout C v dd ov dd enc + adc- shdn rand mode lvds dith ognd enc C input amplifier pga adc reference input s/h control logic output drivers differential input low jitter clock driver internal clock signals in + in C sense ampshdn v cc d15 d0 of + of C anti-alias filter first pipelined adc stage voltage reference dither signal generator shift register and error correction second pipelined adc stage third pipelined adc stage fourth pipelined adc stage fifth pipelined adc stage pga gnd range select 100
ltm9001-ax/ltm9001-bx 17 9001fc operation dynamic performance definitions signal-to-noise plus distortion ratio the signal-to-noise plus distortion ratio [s/(n+d)] is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the adc output. signal-to-noise ratio the signal-to-noise (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components, except the ? rst ? ve harmonics. total harmonic distortion total harmonic distortion is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency. thd is expressed as: thd = ?20log (v2 2 + v3 2 + v4 2 + ...vn 2 ) /v1 ? ? ? ? where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. intermodulation distortion if the input signal consists of more than one spectral component, the transfer function nonlinearity can produce intermodulation distortion (imd) in addition to thd. imd is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. if two pure sine waves of frequencies fa and fb are applied to the input, nonlinearities in the transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. for example, the 3rd order imd terms include (2fa + fb), (fa + 2fb), (2fa C fb) and (fa C 2fb). the 3rd order imd is de? ned as the ration of the rms value of either input tone to the rms value of the largest 3rd order imd product. spurious free dynamic range (sfdr) the ratio of the rms input signal amplitude to the rms value of the peak spurious spectral component expressed in dbc. sfdr may also be calculated relative to full-scale and expressed in dbfs. aperture delay time aperture delay is the time from when a rising enc + equals the enc C voltage to the instant that the input signal is held by the sample and-hold circuit. aperture delay jitter the variation in the aperture delay time from conversion to conversion. this random variation will result in noise when sampling an ac input. the signal to noise ratio due to the jitter alone will be: snr jitter = C20log (2 ? f in ? t jitter ) description the ltm9001 is an integrated system in a package (sip) module ? receiver that includes a high-speed, sampling 16-bit a/d converter, matching network, anti-aliasing ? lter and a low noise, differential ampli? er with ? xed gain. it is designed for digitizing high frequency, wide dynamic range signals with an intermediate frequency (if) range up to 300mhz.
ltm9001-ax/ltm9001-bx 18 9001fc figure 1. basic functional elements 9001 f01 amplifier adc adc input network operation the following sections describe in further detail the func- tional operation of the ltm9001. the sip technology allows the ltm9001 to be customized and this is described in the ? rst section. the remaining outline follows the basic functional elements as shown in figure 1. technology has in place a program to deliver other speed, resolution, if range, gain and ? lter con? gurations for a wide range of applications. see table 1 for the ltm9001-aa con? guration and potential options. these semi-custom designs are based on existing adcs and ampli? ers with an appropriately modi? ed matching network. the ? nal subsystem is then tested to the exact parameters de? ned for the application. the ? nal result is a fully integrated, accurately tested and reliable solution. for more details on the semi-custom receiver subsystem program, contact linear technology. note that not all combinations of options in table 1 are possible at this time and speci? ed performance may differ signi? cantly from existing values. this data sheet discusses devices with lvds and cmos outputs. the lower speed options that only support cmos outputs are available on a separate data sheet. the cmos-only options have a different pin assignment. amplifier information the ampli? ers used in the ltm9001 are low noise and low distortion fully differential adc drivers. the ampli? ers are very ? exible in terms of i/o coupling. they can be ac- or dc-coupled at the inputs. users are advised to keep the input common mode voltage between 1v and 1.6v for proper operation. if the inputs are ac-coupled, the input common mode voltage is automatically biased. the input signal can be either single-ended or differential with almost no difference in distortion performance. table 1. semi-custom options amplifier if range amplifier input impedance amplifier gain filter adc sample rate adc resolution output part number 300mhz 200 20db 162.5mhz bpf, 50mhz bw 130msps 16-bit lvds/cmos ltm9001-aa 300mhz 200 14db 70mhz bpf, 25mhz bw 130msps 16-bit lvds/cmos ltm9001-ad 300mhz 400 8db dc-300mhz lpf 160msps 16-bit lvds/cmos ltm9001-ba select combination of options from columns below dc-300mhz 50 26db lpf tbd 160msps 16-bit lvds/cmos dc-140mhz 200 20db bpf tbd 130msps 14-bit lvds/cmos dc-70mhz 200 14db 105msps cmos dc-35mhz 400 8db 80msps cmos 200 6db 65msps cmos 40msps cmos 25msps cmos 10msps cmos semi-custom options the module construction affords a new level of ? exibility in application-speci? c standard products. standard adc and ampli? er components can be integrated regardless of their process technology and matched with passive components to a particular application. the ltm9001-aa, as the ? rst example, is con? gured with a 16-bit adc sampling at rates up to 130msps. the ampli? er gain is 20db with an input impedance of 200 and an input range of 233mv p-p . the matching network is designed to optimize the interface between the ampli? er output and the adc under these conditions. additionally, there is a 2-pole bandpass ? lter designed for 162.5mhz 25mhz. however, other options are possible through linear tech- nologys semi-custom development program. linear
ltm9001-ax/ltm9001-bx 19 9001fc input span the ltm9001 is con? gured with a ? xed input span and input impedance. with the ampli? er gain and the adc input network described above for ltm9001-aa, the full- scale input range of the driver circuit is 233mv p-p . the recommended adc input span is achieved by tying the sense pin to v dd . however, the adc input span can be changed by applying a dc voltage to the sense pin. input impedance and matching the differential input impedance of the ltm9001 can be 50, 200 or 400. in some applications the differential inputs may need to be terminated to a lower value imped- ance, e.g. 50, in order to provide an impedance match for the source. several choices are available. one approach is to use a differential shunt resistor (figure 2). another approach is to employ a wide band transformer (figure 3). both methods provide a wide band match. the termination resistor or the transformer must be placed close to the input pins in order to minimize the re? ection due to input mismatch. table 2. differential ampli? er input termination values z in r t fig 2 400 57 200 66.5 50 none 9001 f02 z in /2 r t r f ltm9001 z in /2 25 25 v in r f in + in C + C 9001 f03 z in /2 r f ltm9001 z in /2 25 25 v in r f + C ? ? in + in C figure 2. input termination for differential 50 input impedance using shunt resistor (see table 2 for r t values) figure 3. input termination for differential 50 input impedance using a wideband transformer operation adc input network the passive network between the ampli? er output stage and the adc input stage can be con? gured for bandpass or lowpass response with different cutoff frequencies and bandwidths. the ltm9001-aa, for example, implements a 2-pole bandpass ? lter centered at 162.5mhz with 50mhz bandwidth. note that the ? lter attenuates the signal at 162.5mhz by 1db, making the overall gain of the subsystem 19db. for production test purposes the ? lter is designed to allow dc inputs into the adc. converter information the analog-to-digital converter (adc) is a cmos pipelined multistep converter with a front-end pga. as shown in the functional block diagram, the converter has ? ve pipelined adc stages; a sampled analog input will result in a digitized value seven cycles later (see the timing diagram section). the encode input is differential for improved common mode noise immunity. applications information
ltm9001-ax/ltm9001-bx 20 9001fc applications information 9001 f04 z in /2 0.1f 0.1f r f ltm9001 z in /2 r s 50 r s /r t v in r f + C 0.1f r t in + in C figure 4. input termination for differential 50 input impedance using shunt resistor alternatively, one could apply a narrowband impedance match at the inputs for frequency selection and/or noise reduction. referring to figure 4, ampli? er inputs can be easily con? gured for single-ended input without a balun. the signal is fed to one of the inputs through a matching network while the other input is connected to the same impedance. in general, the single-ended input impedance and termination resistor r t are determined by the combination of r s , z in /2 and r f . table 3. single-ended ampli? er input termination values z in r t fig 4 400 59 200 68.5 50 150 the ltm9001 ampli? er is stable with all source impedances. the overall differential gain is affected by the source impedance in figure 5: a v = | v out /v in | = (1000/(r s + z in /2)) the noise performance of the ampli? er also depends upon the source impedance and termination. for example, an input 1:4 transformer in figure 3 improves the input noise ? gure by adding 6db voltage gain at the inputs. reference and sense pin operation figure 6 shows the converter reference circuitry consisting of a 2.5v bandgap reference, a programmable gain ampli? er and control circuit. there are three modes of reference operation: internal reference, 1.25v external reference or 2.5v external reference. to use the internal reference, figure 5. calculate differential gain 9001 f05 z in /2 r t r f ltm9001 z in /2 r s /2 r s /2 v in r f in + in C + C figure 6. reference circuit pga sense internal adc reference range select and gain control 2.5v bandgap reference tie to v dd to use internal 2.5v reference or input for external 2.5v reference or input for external 1.25v reference 9001 f06 tie the sense pin to v dd . to use an external reference, simply apply either a 1.25v or 2.5v reference voltage to the sense input pin. both 1.25v and 2.5v applied to sense will result in the maximum full-scale range.
ltm9001-ax/ltm9001-bx 21 9001fc applications information pga pin the pga pin selects between two gain settings for the adc front-end. pga = low selects the maximum input span; pga = high selects a 3.5db lower input span. the high input range has the best snr. for applications with high linearity requirements, the low input range will have improved distortion; however, the snr will be 1.8db worse. see the typical performance characteristics section. driving the encode inputs the noise performance of the converter can depend on the encode signal quality as much as the analog input. the encode inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 6k resistor to a 1.6v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequencies), take the following into consideration: 1. differential drive should be used. 2. use the largest amplitude possible. if using transformer coupling, use a higher turns ratio to increase the am- plitude. 3. if the adc is clocked with a ? xed frequency sinusoidal signal, ? lter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs such that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to v dd . each input may be driven from ground to v dd for single-ended drive. the encode clock inputs have a differential 100 input impedance. for 50 inputs e.g. signal generators, an additional 100 impedance will provide an impedance match, as shown in figure 7b. maximum and minimum encode rates the maximum encode rate for the ltm9001-ax is 130msps and 160msps for ltm9001-ba. for the adc to operate properly the encode signal should have a 50% (5%) duty cycle. each half cycle must have at least 3.65ns (ltm9001-ax, or 2.97ns for ltm9001-ba) for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. when using a single-ended encode signal asymmetric rise and fall times can result in duty cycles that are far from 50%. v dd v dd ltm9001 9001 f07a v dd enc C enc + 100 1.6v 1.6v 6k 6k to internal adc clock drivers 50 8.2pf 0.1f 0.1f 0.1f t1 t1 = m/a-com etc1-1-13 50 ltm9001 9001 f07b enc C enc + 100 ? ? figure 7a. equivalent encode input circuit figure 7b. transformer driven encode
ltm9001-ax/ltm9001-bx 22 9001fc applications information an optional clock duty cycle stabilizer can be used if the input clock does not have a 50% duty cycle. this circuit uses the rising edge of enc to sample the analog input. the falling edge of enc is ignored and an internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 30% to 70% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin must be connected to 1/3v dd or 2/3v dd using external resistors. the lower limit of the sample rate is determined by the droop of the sample and hold circuits. the pipelined ar- chitecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the speci? ed minimum operating frequency for the ltm9001 is 1msps. digital outputs digital output modes the ltm9001 can operate in four digital output modes: standard lvds, low power lvds, full rate cmos, and demultiplexed cmos. the lvds pin selects the mode of operation. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistive divider can be used to set the 1/3v dd and 2/3v dd logic levels. table 4 shows the logic states for the lvds pin. table 4. lvds pin function lvds digital output mode 0v(gnd) full-rate cmos 1/3v dd demultiplexed cmos 2/3v dd low power lvds v dd lv d s digital output buffers (cmos modes) figure 10 shows an equivalent circuit for a single output buffer in cmos mode, full-rate or demultiplexed. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and eliminates the need for external damping resistors. 9001f8 enc C 1.6v v threshold = 1.6v enc + 0.1f ltm9001 figure 8. single-ended enc drive, not recommended for low jitter figure 9. enc drive using a cmos to pecl translator 9001 f09 enc C enc + 3.3v 3.3v 165 165 261 261 d0 q0 q0 mc100lvelt22 ltm9001 100 9001 f10 ov dd v dd v dd typical data output ognd 43 ov dd 0.5v to 3.6v predriver logic data from latch ltm9001 figure 10. equivalent circuit for a digital output buffer
ltm9001-ax/ltm9001-bx 23 9001fc applications information as with all high speed/high resolution converters, the digital output loading can affect the performance. the digital outputs of the ltm9001 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. the output should be buffered with a device such as an alvch16373 cmos latch. for full speed operation the capacitive load should be kept under 10pf. a resistor in series with the output may be used but is not required since the adc has a series resistor of 43 on chip. lower ov dd voltages will also help reduce interference from the digital outputs. digital output buffers (lvds modes) figure 11 shows an equivalent circuit for an lvds output pair. a 3.5ma current is steered from out + to out C or vice versa, which creates a 350mv differential voltage across the 100 termination resistor at the lvds receiver. a feedback loop regulates the common mode output volt- age to 1.2v. for proper operation each lvds output pair must be terminated with an external 100 termination resistor, even if the signal is not used (such as of + /of C or clkout + /clkout C ). to minimize noise the pc board traces for each lvds output pair should be routed close together. to minimize clock skew all lvds pc board traces should have about the same length. in low power lvds mode 1.75ma is steered between the differential outputs, resulting in 175mv at the lvds receivers 100 termination resistor. the output common mode voltage is 1.2v, the same as standard lvds mode. data format the ltm9001 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. this pin has a four level logic input, centered at 0, 1/3v dd , 2/3v dd and v dd . an external resistive divider can be used to set the 1/3v dd and 2/3v dd logic levels. table 5 shows the logic states for the mode pin. table 5. mode pin function mode output format clock duty cycle stabilizer 0v(gnd) offset binary off 1/3v dd offset binary on 2/3v dd 2s complement on v dd 2s complement off over? ow bit an over? ow output bit (of) indicates when the converter is overranged or underranged. in cmos mode, a logic high on the ofa pin indicates an over? ow or under? ow on the a data bus, while a logic high on the ofb pin indicates an over? ow on the b data bus. in lvds mode, a differential logic high on of + /of C pins indicates an over? ow or under? ow. figure 11. equivalent output buffer in lvds mode 9001 f11 3.5ma 1.20v lvds receiver ognd 10k 10k v dd v dd ov dd 3.3v predriver logic data from latch + C ov dd ov dd 43 43 100 ltm9001
ltm9001-ax/ltm9001-bx 24 9001fc applications information output clock the adc has a delayed version of the encode input available as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal encode. in both cmos modes, a bus data will be updated as clk- outa falls and clkoutb rises. in demultiplexed cmos mode the b bus data will be updated as clkouta falls and clkoutb rises. in full rate cmos mode, only the a data bus is active; data may be latched on the rising edge of clkouta or the falling edge of clkoutb. in demultiplexed cmos mode clkouta and clkoutb will toggle at 1/2 the frequency of the encode signal. both the a bus and the b bus may be latched on the rising edge of clkouta or the falling edge of clkoutb. digital output randomizer interference from the adc digital outputs is sometimes unavoidable. interference from the digital outputs may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can result in discernible unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized, trading a slight increase in the noise ? oor for a large reduction in unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied; that is, an exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout output are not affected. the output randomizer function is active when the rand pin is high. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same power supply as for the logic being driven. for figure 12. functional equivalent of digital output randomizer figure 13. derandomizing a randomized digital output ? ? ? clkout of d15/d0 d14/d0 d2/d0 d1/d0 d0 d0 d1 rand = high, randomizer enabled d2 d14 d15 of clkout rand 9001 f12 ltm9001 ? ? ? d1 d0 d2 d14 d15 pc board fpga clkout of d15 d0 d14 d0 d2 d0 d1 d0 d0 9001 f13 ltm9001
ltm9001-ax/ltm9001-bx 25 9001fc example, if the converter is driving a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any logic voltage up to the 3.6v. ognd can be powered with any voltage from ground up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . internal dither the ltm9001 is a 16-bit receiver subsystem with a very linear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. small errors in the transfer function are usually a result of adc element mismatches. an optional internal dither mode can be enabled to randomize the input location on the adc transfer curve, resulting in improved sfdr for low signal levels. as shown in figure 14, the output of the sample-and-hold ampli? er is summed with the output of a dither dac. the dither dac is driven by a long sequence pseudo-random number generator; the random number fed to the dither dac is also subtracted from the adc result. if the dither dac is precisely calibrated to the adc, very little of the dither signal will be seen at the output. the dither signal that does leak through will appear as white noise. the dither applications information figure 14. functional equivalent block diagram of internal dither circuit in C in + s/h amp digital summation output drivers multibit deep pseudo-random number generator 16-bit pipelined adc core precision dac clock/duty cycle control clkout of d15 ? ? ? d0 enc + dither enable high = dither on low = dither off dith enc C 9001 f14 ltm9001 dac will cause a small elevation in the noise ? oor of the adc, as compared to the noise ? oor with dither off. for best noise performance with the dither signal on, the driving impedance connected across pins in + /in C should closely match that of the module (see table 1). a source impedance that is resistive and matches that of the module within 10% will give the best results. supply sequencing the v cc pin provides the supply to the ampli? er and the v dd pin provides the supply to the adc. the ampli? er and the adc are separate integrated circuits within the ltm9001; however, there are no supply sequencing considerations beyond standard practice. it is recommended that the ampli? er and adc both use the same low noise, 3.3v supply, but the ampli? er may be operated from a lower voltage level if desired. both devices can operate from the same 3.3v linear regulator but place a ferrite bead between the v cc and v dd pins. separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies.
ltm9001-ax/ltm9001-bx 26 9001fc applications information grounding and bypassing the ltm9001 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltm9001 has been optimized for a ? ow-through layout so that the interaction between inputs and digital outputs is minimized. a continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. the ltm9001 is internally bypassed with the ampli? er (v cc ) and adc (v dd ) supplies returning to a common ground (gnd). the digital output supply (0v dd ) is returned to ognd. additional bypass capacitance is optional and may be required if power supply noise is signi? cant. the differential inputs should run parallel and close to each other. the input traces should be as short as possible to minimize capacitance and to minimize noise pickup. heat transfer most of the heat generated by the ltm9001 is transferred through the bottom-side ground pads. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of suf? cient area with as many vias as possible. recommended layout the high integration of the ltm9001 makes the pc board layout very simple and easy. however, to optimize its electri- cal and thermal performance, some layout considerations are still necessary, see figures 15-18. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. common ground (gnd) and output ground (ognd) are electrically isolated on the ltm9001, but can be connected on the pcb underneath the part to provide a common return path. ? use multiple ground vias. using as many vias as pos- sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as pos- sible, using vias to create high-frequency barriers. this will reduce digital feedback that can reduce the signal-to-noise ratio (snr) and dynamic range of the ltm9001. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in application note 100. the ltm9001 employs gold-? nished pads for use with pb-based or tin-based solder paste. it is inherently pb-free and complies with the jedec (e4) standard. the materi- als declaration is available online at http://www.linear. com/designtools/leadfree/mat_dec.jsp.
ltm9001-ax/ltm9001-bx 27 9001fc applications information figure 15. layer 1 figure 17. layer 3 figure 16. layer 2 figure 18. layer 4
ltm9001-ax/ltm9001-bx 28 9001fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description lga package 81-lead (11.25mm 11.25mm 2.32mm) (reference ltc dwg # 05-08-1809 rev a) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 and spp-020 5. primary datum -z- is seating plane 6. the total number of pads: 81 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or a marked feature symbol aaa bbb tolerance 0.15 0.10 11.250 bsc package top view lga 81 1107 rev a 11.250 bsc 4 pad 1 corner 3 pads see notes x y aaa z aaa z 2.17 ?2.47 detail a package side view detail a substrate mold cap 0.27 ?0.37 1.90 ?2.10 bbb z z 1.27 bsc 0.605 ?0.665 0.25 45 chamfer 3 0.605 ?0.665 10.160 bsc 10.160 bsc pad 1 6 7 8 951 2 3 4 package bottom view 5.080 5.080 3.810 3.810 2.540 2.540 0.000 1.270 1.270 0.9525 1.5875 5.080 2.540 3.810 5.080 3.810 1.270 2.540 1.270 0.000 1.5875 0.9525 suggested pcb layout top view ltmxxxxxx module tray pin 1 bevel component pin ?1 package in tray loading orientation j h b a d c e f g
ltm9001-ax/ltm9001-bx 29 9001fc revision history rev date description page number c 7/10 updated timing characteristics section 6, 7 (revision history begins at rev c)
ltm9001-ax/ltm9001-bx 30 9001fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0710 rev c ? printed in usa related parts part number description comments ltc2202 16-bit, 10msps adc 140mw, 81.6db snr, 100db sfdr ltc2203 16-bit, 25msps adc 220mw, 81.6db snr, 100db sfdr ltc2204 16-bit, 40msps adc 480mw, 79.1db snr, 100db sfdr ltc2205 16-bit, 65msps adc 610mw, 79db snr, 100db sfdr ltc2206 16-bit, 80msps adc 725mw, 77.9db snr, 100db sfdr ltc2207 16-bit, 105msps adc 900mw, 77.9db snr, 100db sfdr ltc2208 16-bit, 130msps adc 1250mw, 77.7db snr, 100db sfdr ltc2209 16-bit, 160msps adc 1450mw, 77.1db snr, 100db sfdr ltc6400-8/ltc6400-14/ ltc6400-20/ltc6400-26 low noise, low distortion differential ampli? er for 300mhz if, fixed gain of 8db, 14db, 20db or 26db 3v, 90ma, 39.5dbm oip3 at 300mhz, 6db nf ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 low noise, low distortion differential ampli? er for 140mhz if, fixed gain of 8db, 14db, 20db 20db or 26db 3v, 45ma, 45.5dbm oip3 at 140mhz, 6db nf 0v 75 r s 50 9001 ta02 groundC referenced source + C 75 51.1 3.3v v cc ltm9001 in + in C ltm9001 with ground-referenced single-ended input typical application

▲Up To Search▲

Price & Availability of LTM9001-AX10

	To Download LTM9001-AX10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .